1. Field of the Invention
The present invention relates to an electrostatic protection element to be mounted onto a semiconductor integrated circuit device, and particularly relates to an electrostatic protection element having a thyristor structure.
2. Description of the Related Art
Recently, in association with miniaturization and high integration of a pattern in a semiconductor integrated circuit device, an electrostatic protection element for protecting a semiconductor integrated circuit device from static electricity that electrically charges a human body or machines also requires miniaturization. The electrostatic protection element is connected to an Input/Output terminal or a power supply terminal of the semiconductor integrated circuit device. When surges are applied to the I/O terminal and the power supply terminal, an influx of a surge current by the surges into an internal circuit that is a target for protection (a circuit to be protected) is prevented. This type of electrostatic protection element is also referred to as ESD (electro static discharge) protection element, and an NPN bipolar transistor and a thyristor structure are variously proposed.
When the electrostatic protection element is composed of the same constituent elements as those of the internal element comprising the internal circuit, the electrostatic protection element can be simultaneously manufactured in the same process as the internal element. For example, when the internal circuit includes an NPN bipolar transistor (hereafter, referred to as NPN transistor), the NPN transistor is often used as the electrostatic protection element. However, because so-called holding voltage Vh (collector emitter junction breakdown voltage (BVCEO) in the base opened state) in the snapback characteristic of the NPN transistor is small, when the internal circuit contains a high breakdown voltage semiconductor element and a low breakdown voltage semiconductor element, the holding voltage Vh tends to be lower than a breakdown voltage of the high breakdown voltage semiconductor element. Consequently, the NPN transistor is hardly used for a use of the protection of the high breakdown voltage semiconductor element.
However, recently, a structure of the NPN transistor where the holding voltage Vh has been improved is proposed, and the NPN transistor has become used for the electrostatic protection of the high breakdown voltage semiconductor element. For example, Japanese Laid-Open Patent Application Publication No. 2006-128293 discloses the structure of the NPN transistor for electrostatic protection that is equipped with a deep high-concentration N-type diffusion layer in a collector contact region. FIG. 10 is a cross sectional view showing the electrostatic protection element of the semiconductor integrated circuit device disclosed in this conventional art.
As shown in FIG. 10, the NPN transistor for electrostatic protection is provided with a low-concentration N-type diffusion layer 103 (hereafter, referred to as N−−-type diffusion layer 103) formed in a P-type semiconductor substrate 101. A P-type diffusion layer 105 to be a base of the NPN transistor is formed in a surface portion of the N−−-type diffusion layer 103, and a high-concentration N-type diffusion layer 106 (hereafter, referred to as N++-type diffusion layer 106) to be an emitter of the NPN transistor is formed in a surface portion of the P-type diffusion layer 105. Further, a high-concentration N-type diffusion layer 104 (hereafter, referred to as N+-type diffusion layer 104) constructing a part of a collector region of the NPN transistor is formed in the N−−-type diffusion layer 103 spaced apart from the P-type diffusion layer 105 laterally at a predetermined distance to be deeper than the P-type diffusion layer 105 and throughout the depth to reach the P-type semiconductor substrate 101.
A P-type separating layer composed of a low-concentration P-type diffusion layer 102 (hereafter, referred to as P−-type diffusion layer 102) and a high-concentration P-type diffusion layer 110 formed in a surface portion of the P−-type diffusion layer 102 is located around a circumference of the N−−-type diffusion layer 103. Further, a high-concentration P-type diffusion layer 107 (hereafter, referred to as P+-type diffusion layer 107) for ohmic contact and a high-concentration N-type diffusion layer 109 (hereafter, referred to as N++-type diffusion layer 109) are formed in the contact region of the P-type diffusion layer 105 and the contact region of the N+-type diffusion layer 104, respectively.
In the NPN transistor for electrostatic protection having the configuration described above, as shown in FIG. 10, the P+-type diffusion layer 107, which is a base contact, and the N++-type diffusion layer 106, which is the emitter, are short-circuited by an aluminum wire and connected to the lowest potential, such as GND (grounding potential). Further, the N++-type diffusion layer 109, which is a collector contact, is connected to an I/O terminal 130 (hereafter, referred to as I/O PAD 130) and an internal circuit 140 formed on the semiconductor substrate 101, by an aluminum wire. Herein, the internal circuit 140 is a circuit composed of the internal elements and is a target circuit for protection to realize a function of the semiconductor integrated circuit device.
Next, a phenomenon in a case of applying a plus surge to the semiconductor integrated circuit device provided with the NPN transistor for electrostatic protection having the above configuration from the I/O PAD 130 is explained with reference to FIGS. 10 and 11. FIG. 11 shows current-voltage characteristics of the NPN transistor for electrostatic protection shown in FIG. 10. In FIG. 11, the horizontal axis corresponds to a collector potential, and the vertical axis corresponds to a collector current.
When the plus surge is applied to the I/O PAD 130, due to a rise of the collector potential, avalanche breakdown occurs especially in a region with great curvature at a collector-base PN-junction composed of the P-type diffusion layer 105 and the N−−-type diffusion layer 103 (BVCBO in FIG. 11). When the breakdown occurs, current due to the breakdown flows into the P-type diffusion layer 105. The potential (base potential) of the P-type diffusion layer 105 rises by the current and resistance of the P-type diffusion layer 105 itself. Then, when the collector potential further rises due to the plus surge, the base potential reaches an on-voltage of the NPN transistor, and the NPN transistor starts a bipolar action (trigger point (Vtr, Itr) in FIG. 11).
When the NPN transistor starts the bipolar action, a large amount of electrons are injected from the N++-type diffusion layer 106 to the N−−-type diffusion layer 103. In the configuration shown in FIG. 10, because impurity concentration of the N−−-type diffusion layer 103 immediately under the N++-type diffusion layer 106 is comparatively low, the electrons injected from the N++-type diffusion layer 106 become excess in the N−−-type diffusion layer 103. In order to neutralize these excess electrons, holes are injected from the P-type diffusion layer 105. The N−−-type diffusion layer 103 region immediately under the N++-type diffusion layer 106 starts acting like a base due to the injection of the holes. At this time, since the N−−-type diffusion layer 103 becomes not an N-type layer but a neutral region with regard to a carrier charge, effective resistance with regard to the current are decreased and the collector potential is lowered. The state is a state where the NPN transistor is saturated. As a result, the collector potential is decreased from the trigger voltage Vtr to the holding voltage Vh, which is a value depending upon a grounded-emitter DC current gain (hereafter, simply referred to as a current gain hFE) of the NPN transistor in the saturated state.
Further, at this time, the neutral region of the N−−-type diffusion layer 103 reaches to the P-type semiconductor substrate 101, and a part of the P-type semiconductor substrate 101 is also operated as a base as similar to the N−−-type diffusion layer 103 immediately under the N++-type diffusion layer 106. Therefore, because an apparent base width becomes very wide, the current gain hFE becomes smaller, and the holding voltage Vh is maintained at high. Such expansion of the base region occurs to a boundary between the P-type semiconductor substrate 101 and the N−−-type diffusion layer 103 due to not forming an N-type buried diffusion layer with high impurity concentration in the NPN transistor for electrostatic protection.
Furthermore, when the holding voltage Vh of the NPN transistor for electrostatic protection is lower than an operating upper limit voltage VA (voltage defined with maximum voltage for effectively operating the internal elements comprising the internal circuit 140 or maximum rating) of the internal circuit 140, input of instantaneous noises at the time of normally operating the semiconductor integrated circuit device shall cause the bipolar action of the NPN transistor for electrostatic protection. In this case, a signal to be entered from the I/O PAD 130 will not be entered into the internal circuit 140, and the semiconductor integrated circuit device cannot be normally operated. Further, when the NPN transistor for electrostatic protection is connected to the power supply terminal, the collector is fixed to the operating supply voltage of the internal circuit 140, and the NPN transistor for electrostatic protection breaks down by an excess supply current from a power source. Consequently, the holding voltage Vh of the NPN transistor for electrostatic protection is required to be the operating upper limit voltage VA of the internal circuit 140 or greater.
After the collector potential is decreased to the holding voltage Vh, the collector potential continues to rise according to the collector resistance depending upon the collector N+-type diffusion layer 104 from the holding voltage Vh to breakdown potential Vt2 in association with the increase in the collector current (bipolar action region shown in FIG. 1). In the configuration shown in FIG. 10, since the impurity concentration of the N+-type diffusion layer 104 in the collector region is high, the N+-type diffusion layer 104 continuously functions as a collector without becoming a base in the holes injected from the P-type diffusion layer 105. Then, after the breakdown voltage Vt2 is reached, heat generation within the NPN transistor causes thermal runaway and thermal destruction occurs (breakdown point (Vt2, It2) in FIG. 11).
In the NPN transistor with the motion described above, the breakdown voltage Vt2 is irreversible breakdown voltage VB of the internal elements constituting the internal circuit 140 or less, and since the holding voltage Vh will never be the operating upper limit voltage VA or less, the NPN transistor can be used as the electrostatic protection element for protecting high breakdown voltage semiconductor element.